Single event effect mitigation for silicon-on-insulator CMOS technology

A circuit and method for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary MetalOxideSemiconductor (CMOS) integrated circuits, in which a primary logic output 122 is generated from a primary logic gate 102 in response to an input 126, 128; a redundant logic output 124 is generated from a redundant logic gate 104 that duplicates the primary logic output in response to the input if an SEE is not present and an interleaved C-gate output 130 is generated from an interleaved C-gate 106 that emulates an inverter output when the primary logic output and the redundant logic output match, and does not change its output when the primary logic output and the redundant logic output do not match during the SEE.