Delay and area efficient approximate multiplier using reverse carry propagate full adder

Abstract The performance and power of error resilient applications will rise with a decrease in designing complexness due to approximate computing. This paper includes the new method for the approximation of multipliers. Variable likelihood terms are produced by the alteration of partial products of the multiplier. Based on the probability statistics, the accumulation of altered partial products leads to the variation of logic complexity. Here the estimate is implemented in 2 variables of 16-bit multiplier and in the final stage with reverse carry propagate adder(RCPA). The reverse carry propagate adder have carry signal propagation from the most significant bit(MSB) to the least significant bit(LSB), which results in greater relevance to the input carry than the output carry. The technique of carry circulation in reverse order with delay variations increases the stability. Utilizing the RCPA in approximate multiplier provide 21% and 7% improvements in area and delay. On comparing, this structure is resilient to delay variations than the ideal approximate adder.