A new wafer level chip size MCM-D technology for cellular applications

A wafer level chip size MCM-D technology has been developed. It is characterised by its unique top-to-bottom connection procedure. This allows connecting the top-interconnect towards the bottom-side, where a ball grid array (BGA) pattern is made. To realise this, processing on wafers with a 3-D structure was required. This is accomplished by using a mix of IC processing and printed-circuit board techniques. The technology starts with a silicon substrate that accommodates a number of integrated passive functions and high density interconnect. Throughout the process this intelligent substrate is used as the carrier. In this silicon wafer vias are made through the wafer using a powder blasting technique. After an isolation step, a Cu metal layer is applied on top, bottom and vias of the wafer. Using 3-D lithographic techniques the metal is patterned in one step, creating the connection on the topside, defining multiple top-to-bottom tracks in the slots, and forming a BGA metal pattern on the backside of the wafer. A screen printing technique followed by a reflow step is used to form BGA solder balls on the backside of the wafer. At this point the wafer/substrate is ready for mounting flip chip ICs. Sawing can be done after the final assembly. A number of test devices have been realised. The potential of the technology, in terms of maximal miniaturisation, integrated functionality, and electrical performance will be demonstrated for a Voltage controlled oscillator module to be used in the transmit path in a cellular phone handset (TXVCO). This TXVCO module consists of a silicon based carrier with integrated inductors, capacitors and resistors, a flip chip functional RF IC and a 2nd level interconnect formed by an area array BGA connection. Functional modules have been mounted on RF test boards, and tested.