Design of an Improved Low-Power and High-Speed Booth Multiplier

This paper presents an improved 8 × 8-bit Booth multiplier with reduced power, delay and area. The major operations that consume power and are responsible for larger critical path delays in Booth multiplication are partial product array generation (PPAG), partial product array compression (PPAC) and partial product array addition (PPAA), for the generation of the final product. So, in our proposed multiplication framework, the design improvements are focused on B-to-C, PPAG, PPAC and PPAA. For speed-power improvement in PPAG operations, an improved circuit for binary-to-two’s complement converter has been proposed to provide a lower critical path delay. Secondly, for power-area improvement, we have proposed a new scheme to generate the first term for all PPAs, the encoder for the generation of the first partial product array (PPA) and modified encoders for third PPA. This results in reduced multiplexer sizes, leading to lower power consumption and lower delays during PPAG. For speed-power improvement in the partial product array addition (PPAA), the carry save addition scheme without carry propagation has been proposed for the reduction of partial product arrays that speeds up the PPAC operation. For the final addition of the last two operands, i.e. PPAA, an n-bit adder segment is designed for our proposed 13-bit modified carry select adder (MCSA) that provides a major contribution in the speed-power and area efficiency of the proposed Booth multiplier architecture. The proposed architecture along with some recently reported state-of-the-art architectures is implemented in 1P-9 M Low K 90-nm CMOS technology, and simulations are carried out using Cadence Virtuoso using 500 MHz clock pulse frequency at a temperature of 27 °C using supply voltage of 1.25 V, for comparison purposes. The proposed multiplier provides an improvement of 26.12% in delay, 32.9% improvement in power-delay product and 32.36% improvement in area-delay product, as compared to the recent designs.