Implication of polarity dependence degradation on NMOSFET with polysilicon/Hf-silicate gate stack

Previously, the polarity dependence of stress induced dielectric wearout has been reported in NMOSFETs with a poly-Si/HfSiO gate stack. In the case of positive bias stress (substrate injection), electrons can be trapped in the high-k layer resulting in a shift of the threshold voltage with minimal degradation of the interface quality. On the other hand, negative gate bias stress induces significant interface degradation. Interface defects generated by the negative gate voltage stress increase the gate leakage at a bias near the threshold voltage region and degrade the subthreshold swing. In this work, the polarity dependence effects in NMOS transistors are re-visited to investigate in detail how the device characteristics are affected by these effects.