Highly Extendible Memory Cell Architecture for Reliable Data Retention Time for 0.10mm Technology Node and beyond

In this paper, data retention time has been investigated for the high speed and low power 512Mb DRAM (Dynamic Random Access Memory) with 0.10Pm design rule. As the technology generation of DRAM has been developed into sub-quarter micron regime, the control of junction leakage current at storage node is much more important due to the increased channel doping concentration. In order to obtain high performance DRAM with design rule 0.10Pm, novel SAC (Self Aligned Contact) process using SRP (SAC spacer Removal after Plug implantation) is developed to improve data retention time characteristic and minimize short channel effect in cell transistor. We also tried to cure the surface defect and minimize junction leakage current using gate dual spacer and DS (Down Stream) surface cleaning process. The high capacitance is realized by DMO (Dual Molded Oxide) capacitor process. This novel storage node structure gives much better mechanical stability of capacitor. With novel cell architecture, the dramatic increase of data retention time and device yield for 512Mb DRAM can be obtained. The developed cell architecture can be fairly extendible to the future high density DRAM beyond 0.10Pm technology node.