Modular Minicomputers Using Microprocessors

This paper presents the design and breadboard implementation of an experimental multiprocessor (mP) whose objectives were 1) to provide modularity of performance over the range of 0.2 million instuctions/s (mips) to about 3 mips and 2) to optimize cost-performance over this selected range by exploiting the high technology of microprocessors and RAM's. The design was aimed at applications with inherent parallelism, such as those employing multiuser interactive or multistream batch processing, and avoided dependencies on problem decomposition per se. Measurements on a breadboard version showed that in suitable batch processing environments, an eight processor system could achieve a throughput that was 6.5 times greater than that of a single component processor. They also showed that on increasing the number of users in interactive environments, the behavior of the mP was similar to that of an uniprocessor of like throughput. However, the response time seen in any given application would betray the speed of the constituent microprocessor relative to that of the uniprocessor, in proportion to the amount of direct processor activity involved in that application. The hardware design included an mP switch element comprised of a time-multiplexed pipeline whose heart was a common cache serving all the processors. The software design was based on minor modifications to an existing real-time multiprogramming OS. Software contention losses due to the global interlock used within the shared single-threaded executive were surprisingly small. This paper contains an extensive discussion on hardware and software contention. It highlights the limitations of the chosen techniques and identifies some environments for which they seem well-suited, as well as some for which they are not. Finally, it indicates areas where more work is needed.