Extraction of a lumped element, equivalent circuit model for via interconnections in 3-D packages using a single via structure with embedded capacitors

A methodology for extracting an accurate, lumped element, equivalent circuit model for an interlayer via in a 3-D packaging scheme is presented. The model of a single via is extracted based upon the EM simulation of a test structure in which the via is landed at an internal capacitance layer within the multi-layer Liquid Crystal Polymer (LCP) or Printed Circuit Board (PCB) substrate. The objectives for the single via modeling is to: (i) realize a simplified model that can be used for circuit simulation; (ii) to drastically reduce computation time and; (iii) most importantly, to predict the electrical behavior of the embedded capacitor layer on which the via is terminated. It can be seen from the simulation results that the parasitic inductance and resistance of the via increase with increasing via height. Model as well as EM simulations for via interconnections on the LCP substrate with different via heights (2 mil to 10 mil) have been performed and the model results show good agreement with the EM simulations. For experimental validation, a test structure consisting of a 3 mil thick PCB dielectric on top of a buried 16 micron thick capacitance layer was designed and fabricated. A via diameter of 6 mil was simulated for various internal capacitances of 1, 7, 14, 72, and 142 pF. The model showed good matching with the measured data in the range of 500 MHz to 12 GHz. Therefore, it is evident that simple and precise via modeling can accurately pre-determine the electrical performance of the PCB compatible embedded capacitors which would add immense value to application-driven PCB manufacturing.