NPN tube structure for reducing emitter resistance in polycrystalline silicon emitter BiCMOS process

The invention discloses an NPN tube structure for reducing the emitter resistance in the polycrystalline silicon emitter BiCMOS process. Doping impurities of an N+diffusion region are injected into the composite gate structure polycrystalline silicon surface of a formed longitudinal NPN tube emitter, and the size of the injection region is larger than or equal to the photoetching feature size of the BiCMOS process. According to the NPN tube structure, on the premise that the manufacturing cost is not increased and the device performance is not sacrificed, the emitter resistance of a polycrystalline silicon emitter longitudinal NPN triode is greatly reduced, and the emitter resistance can be linearly reduced along with increasing of the area of an emitter region. The NPN tube structure can effectively have the functions of simplifying the artificial circuit design, improving the circuit performance and improving the product competitiveness.