Nanoscale lift-off process using field emission scanning probe lithography

Nanoelectronics manufacturing requires an ongoing development of lithography and also encompasses some “unconventional” methods. In this context, the authors use field emission scanning probe lithography (FE-SPL) to generate nanoscaled electronic devices. For the generation of future novel quantum devices, such as single-electron transistors or plasmonic resonators, patterning of features in the sub-10 nm regime as well as a defined metallization is necessary. In terms of metallization, the authors take advantage of the well-known lift-off process for creating narrow gap junctions. Narrow gap electrodes have found wide approval in the formation of narrow gap junctions and can be employed for the investigation of the electrical properties of molecules. In the lift-off process presented here, two sacrificial layers (50 nm polymethylglutarimide and 10 nm calixarene) have been deposited and patterned by FE-SPL. Subsequently, the sample was treated with tetraethyl-ammonium hydroxide in order to ensure an undercut. Afterward, a layer of 10 nm thick Cr has been deposited on top and finally the sacrificial films have been removed, leaving behind only the chromium film deposited directly on the substrate. In this work, the authors will present the utilization of novel active cantilevers with diamond coated silicon tips for FE-SPL purposes in order to generate chromium metal features by lift-off for the generation of future quantum devices. In this context, they will present the integration of an ultrananocrystalline diamond (UNCD) layer deposited on the tip of an active silicon cantilever. Electron emission and FE-SPL capabilities of UNCD coated silicon tips are evaluated. The authors demonstrate a reliable fabrication scheme of sub-15 nm coplanar narrow gap metal electrodes.Nanoelectronics manufacturing requires an ongoing development of lithography and also encompasses some “unconventional” methods. In this context, the authors use field emission scanning probe lithography (FE-SPL) to generate nanoscaled electronic devices. For the generation of future novel quantum devices, such as single-electron transistors or plasmonic resonators, patterning of features in the sub-10 nm regime as well as a defined metallization is necessary. In terms of metallization, the authors take advantage of the well-known lift-off process for creating narrow gap junctions. Narrow gap electrodes have found wide approval in the formation of narrow gap junctions and can be employed for the investigation of the electrical properties of molecules. In the lift-off process presented here, two sacrificial layers (50 nm polymethylglutarimide and 10 nm calixarene) have been deposited and patterned by FE-SPL. Subsequently, the sample was treated with tetraethyl-ammonium hydroxide in order to ensure an under...