SiGe HBT / CMOS process thermal budget co-optimization in a 55-nm CMOS node

This paper deals with the reduction of the process thermal budget in a 55-nm BiCMOS technology for improving SiGe HBTs transit frequency, f T . Since MOSFETs are directly impacted by this modification, process adjustments are implemented to recover performances and parametric yield. Spike annealing temperature reduction, thermal re-oxidation replacement and Dynamic Surface Annealing implementation are discussed. A 355 GHz F t / F Max HBT compatible with current 55-nm MOSFET models is demonstrated.