Bottom-up methodology for predictive simulations of self-heating in aggressively scaled process technologies

We present a hierarchical methodology using a combination of ab-initio phonon scattering, electron transmission, and multi-scale finite element simulations to accurately model process specific material physics and component level self-heating in FinFET technologies. The framework is applied to explain key heat transfer pathways and thermal resistance of FinFETs, interconnects and integrated precision resistors. Excellent agreement with thermal resistance measurements and its dependence on process technology is demonstrated across many device types without any fitting. The proposed methodology enables rapid systematic evaluation and process mitigation of self-heating in advanced CMOS technologies.