Method for carrying out optimized speed classification for digital integrated circuit with transparent latch

The invention relates to a method for carrying out optimized speed classification for a digital integrated circuit with a transparent latch under the effect of process deviation, which belongs to the field of integrated circuits and comprises the following steps; computing the minimum clock cycle accumulative density distribution function of the digital integrated circuit with the transparent latch and determining an optimal clock cycle classification demarcation point and an optimal test sequence of the demarcation point according to the minimum clock cycle accumulative density distribution function to maximize the total income. The method can obtain the work clock cycle distribution of the transparent latch circuit through a random configuration method based on very low computation complexity and very high solution accuracy to avoid the convergence problem in a random arrival time solution; the optimal test sequence of the cycle classification demarcation point can be determined through an optimization method of which computation complexity only is 0 (n log n) so as to minimize the test cost; and when the position of the cycle classification demarcation point is determined by a greedy algorithm to maximize the circuit design income, the optimality of each iterative computation can be ensured in theory.