Performance of CMOS differential circuits

Differential CMOS logic family has potential advantages over the standard static CMOS logic family implemented using NAND/NOR logic. These circuits tend to be faster and require fewer transistors. In this paper, various static and dynamic circuit techniques from the differential logic family are evaluated using application circuits like adders and multipliers. Circuits with self-timed characteristics are also considered. Evaluations are performed in terms of area, number of transistors, and propagation delay. Results indicate that in general, dynamic differential circuit techniques are faster than their conventional static counterparts. Further improvement in circuit performance can be achieved by choosing an appropriate differential structure to match logic structure being implemented. Second, even though the circuit techniques such as differential split-level perform better, they may not be widely accepted mainly because of the increase in circuit complexity and cost. Lastly, the self-timed dynamic differential circuit techniques yield considerable improvement in speed without having the problems of charge distribution or race conditions typically associated with the conventional single-ended domino circuit technique.