First demonstration of sub-0.25m-width emitter InP-DHBTs with > 400 GHz ft and > 400 GHz fmax

We report performance of sub-0.25pm emitter-width InPflnGaAsilnP DHBTs. These are the smallest emitterwidth Ill-V devices reported to date. Measured ft'fmax performance of 406GHd423GHz is the first ever reported for a sub-0.25pm emitter-width DHBT and among the fastest for any DHBTs. With the peakf; and fmw. performance occurring at I, = 8mA (Vch-1.2Sv), this is the lowest power consumption DHBT ever reported with state of the art cutoff frequencies. The as-patterned emitter contact metal width for these devices was 0.25pm and the width of the emitter at the emitter-base junction is less than 0.25pm owing to undercutting of the underlying emitter semiconductor. When comparing with 0.4pm emitter width DHBTs, we find that 0.4pm device has the higher measured f,, 4 2 0 G H z , due to the lower emitter resistance for that emitter layout. Fmsx was highest for the 0.2Spm emitter devices due to lower hasecollector mesa capacitance, Ca, which results from the reduced mesa width. We find this behavior to be consistent with scaling tradeoffs in the design of ultra-fast DHBTs. Introduction The march towards higher complexity, higher performance InP integrated circuits has necessitated continual scaling of emitter widths of InP SHBTs and DHBTs to reduce power consumption in a circuit. As the emitter widths are reduced the rest of the device layout needs to be scaled to avoid degradation of cutoff frequencies that may otherwise result. Performance of mesa-HBTs is usually characterized by the unity-gain cutoff frequencies, ft and f,. Figure1 shows schematic cross-section and Fig.2 shows a scanning electron micrograph (SEM) of a finished device and depict the plan layout of a mesa-HBT. Technological parameters of most interest to a device designer are pointed out in reference to Figuresl&2, but the reader is referred to excellent articles in the literaiure for a more in-depth analysis [1,2]. The first aim for increasing integration density is the reduction in the size of the devices quite simply for the area and power considerations. Performance considerations necessitate reduction of all capacitances as well as electron transit times through the base, q and collector layer, T~ Figure 1 Schematic cross section of hiple-mesa HBT showing various parasitic elements of concern to a device designer. Following equation gives the delay terms involved in determining the f, of the device: At the current state of art, there are trade-offs inherent in the aims of device scaling and nothing comes for free. Novel solutions have been researched to decouple extrinsic performance limiting parasitic elements from the intrinsic device, as described in [3], hut these approaches remain technologically several generations away from reaching state of the art device performance. Conventional mesa device Figure 2 Scanning electron micrograph of a 0.25x4pmZ emitter IrtF'iInGaAsnnP DHBT. 02004 HRL Laboratories, LLC. All "ghts reserved 0-7803-8684-1/04/$20.00 02004 IEEE 22.3.1 IEDM 04-553 figures of merit have been improved greatly on the other hand, with some of recent progress reported by groups from was used, with a narrow-band-gap, highly n-doped, cap layer to minimize emitter contact resistance We used a triple-mesa fabrication process. Emitter metal was defined using electron beam lithography and lift-off University of Illinois and University of Califomia, Santa Barbara [4,5]. When scaling down emitter widths, i.e., the intrinsic part of the device, the extrinsic device must be scaled proportionately. The kT/qI, dependent charging times are inversely proportional to the device current-whereas the mesa capacitances must be charged through K,. In-principle when reducing device size proportionately, the product &,*Ck should stay constant. Practically &, may increase faster than the reduction in Ck due to emitter undercutting during wetetching. While intrinsic Ck scales with emitter width, reduction of extrinsic c b c requires a reduction in the width of base-collector mesa with requisite reduction in the width of the base contacts. Here also it is typical to find base contact resistance increasing faster than the reduction in Ck with negative implications for f, which varies as (Rb*Ck).”’. Reduction in transit time requires scaling down base and collector layers vertically. Reduction in base layer thickness negatively affects base resistance and reduced collector thickness increases Cbc and degrades the breakdown voltage. On the positive side, as reduction in thickness is typically accompanied by increased doping density in the collector, it does improve the maximum current capability of the device. With mesa capacitances highly ~optimized, contribution from base contact pads becomes a significant part of parasitic Cbc. Methods to isolate the base contact pad capacitance, e.g., by use of micro-bridges, have been reported [4 and references within]. Finally, considerations of heat removal are of significant importance in the design of scaled DHBTs operated at high current densities. We point out without much discussion that poor thermal conductivity semiconductor layers, such as InGaAs used as ohmic contact layer in the sub-collector, should be either eliminated or reduced in thickness for effective heat removal [6,7]. Experiment Device layers were grown by MBE on Fe doped SI InP substrates. A composite n+ InPflnGaAs subcollector was used to minimize collector resistance. Operating current, collector capacitance and breakdown voltage were all considered in the design of the collector. We selected collector thickness and doping to yield an open base breakdown voltage, BVcEo, of -5V. Band lineup of the InCaAshP heterojunction results in an un-desirable conduction band spike at the base-collector junction. We employed a quartenary grade to smooth out this conduction band spike. Design of the base layers is driven by the need to reduce the base transit time while keeping extrinsic base resistance and base contact resistance low. A 35nm p+ InGaAs base layer was used to provide a base sheet resistance of -750ohdsq. To reduce the base transit time, the indium mole-fraction was adjusted to provide a field gradient of 50meV across the base. An abrupt heterojunction InP emitter metallization. A conventional hi-layer electron sensitive resist was used to pattem O.25pm-width emitters. The emitter mesa was etched using a combination of dry and wet processing. Anisotropic dry etching was used to minimize undercut and a selective wet etch was used to stop on the InGaAs base. Base contact was aligned to the emitter using electron beam lithography. To minimize base collector capacitance, width of the base contacts was scaled-down and base contact pad was undercut during base-collector mesa etching. To understand the scaling limits and performance trade-offs for the InP DHBT we fabricated devices with 0.4pm, 0.35pm and 0.25pm emitter-width devices with 2pm, 4pm, 6pm and 8pm emitter-lengths for each width. For these ultra-scaled layouts the width of the base metal contact is expected to have significant contribution to base contact resistance and hence the total Rb. In our experiments we have found F, to degrade with reduced base contact width beyond a certain point.