Coupling impact of single ended signals to LVDS interface

The speed of general purpose input output (GPIO) continues to increase as more consumer applications utilize “smart” devices. The low-voltage differential signaling (LVDS) is often times the highest speed that GPIO interface needs to support in the mixture of different single ended signaling pins. Although LVDS is differential and somewhat immune to direct signal coupling from other signals, it is still subject to coupling through a shared power supply noise. A thorough SSN analysis between single ended to differential signals is presented in this paper. To help designing GPIO systems, we have considered different single ended signaling types such as SSTL, LVTTL, etc.