Nonlinear Quantization for In-Sram Multi-Bit MAC Design

In-memory computing arises as a novel computing paradigm aiming to overcome the memory wall bottleneck present in the conventional von Neumann architecture. By integrating the computation within the memory array, i.e., 6T CMOS SRAM array, in-memory computing blocks reduce the time- and energy-consuming data movement between the storage and processing cores, thus improving the energy efficiency and performance. Prior work [1] has focused on realizing the multi-bit multiplication and accumulation (MAC) in-memory operation by quantizing the analog discharge behavior associated with the SRAM bit cell. However, prior work realizes the multi-bit quantization by assuming that the discharge rate is linear to input voltage given a discharge interval. Such overlooking of the discharge nonlinearity associated with SRAM may hinder the design from practical multi-bit quantization. In this paper, we analyze the nonlinearity effect of the SRAM bit cell discharge and propose three optimization guidelines to address the challenges caused by nonlinear discharge. Simulation results validate our proposed methods.