A 64K-neuron 64M-1b-synapse 2.64pJ/SOP Neuromorphic Chip with All Memory on Chip for Spike-based Models in 65nm CMOS

Generally, computer-science-oriented artificial neural networks (ANNs) and neuroscience-oriented spiking neural networks (SNNs) are two main approaches to develop brain-spired non von Neumann computing systems. The goal of exploring complex artificial intelligence (AI) systems demands general neuromorphic hardware platforms compatible with both of them. However, as a result of the obvious differences in their fundamental mathematical expression and coding scheme, many neuromorphic platforms or deep neural network (DNN) accelerators accommodate only one of them. This brief presents a reconfigurable scalable neuromorphic chip based on digital leaky integrate-and-fire (LIF) neuron model targeting low-cost large-scale systems. By unifying ANN and SNN paradigms within a LIF neuron framework with point-to-point (P2P) communication, the chip can accommodate most popular neural networks. The chip adopts distributed on-chip memory architecture with a capacity of 64K neurons and 64M synapses. It achieves a peak throughput of 12.29 GSOP/s at 1.2 V, 192MHz and peak energy efficiency of 2.64 pJ/SOP at 890 mV, 24MHz. The results of implementations of a spike-based spatio-temporal memory model and ternary-weight event-based convolutional neural networks (CNNs) demonstrate outstanding compatibility of the chip.