A Novel Countermeasure Against Differential Scan Attack in AES Algorithm.

The Design for Testability (specifically scan designs) is standard testing techniques for Digital cores for achieving high fault coverage and to provide better controllability and observability. However, such test architectures in the chip containing secret data mostly becomes the instrumental for secret information leakage. The attacker may use different implementation attacks to leak the secret data. In this paper, we first analyse the existing scan designs from security perspective. We demonstrated that how the secret key is retrieved by differential scan attack (DSA) in case of symmetric encryption standards (AES). Furthermore, it is also shown that AES along with time compactor also fails to provide sufficient security. We then propose novel prevention mechanism, Modular Exponentiation Secure Scheme (ME-SS), which clears the insecure states of all the existing techniques. Our experimental results show that the proposed countermeasures can effectively insulate all the information related to cipher key from DSA.