A Low-Power, High-Linearity Wideband 3.25 GS/s Fourth-Order Programmable Analog FIR Filter Using Split-CDAC Coefficient Multipliers

This article presents a 3.25 GS/s fourth-order programmable analog finite impulse response (AFIR) filter for flexible discrete time analog signal processing (DT-ASP). For wide application of the proposed AFIR filter, it is designed for full bandwidth utilization up to the Nyquist rate, programmable via the multiplier coefficient set. In this implementation of the FIR function, split-capacitive DACs (split CDACs) are adopted as coefficient multipliers, providing high-linearity over the full frequency range and low power consumption. Individual coefficients are digitally controlled with total 7-bit codes, consisting of 6-bit fractional value, and 1-bit for sign selection. The addition is simply implemented in the current-domain. Noise and effects of the time-interleaved operation are analyzed to understand limitations on the dynamic range. The proposed AFIR filter is implemented in 32-nm SOI CMOS technology; the core area of the circuit is 0.1 mm 2 . Measurement results demonstrate transfer function configurability over all possible low pass filter (LPF), bandpass filter (BPF), and high pass filter (HPF) linear phase coefficient sets. The AFIR filter achieves > 11-dBm third-order input intercept point (IIP3) over the full frequency range with a 0.9-V supply. The maximum power consumption is 10.6 mW.