A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling

This paper presents a low-power resistive sensor interface circuit with correlated double sampling which reduces the effect of amplifier offset and enables time-interleaved single-to-differential sampling. The proposed sampling scheme, used with a 12b SAR-type analog-to-digital converter, effectively doubles the input signal and improves linearity. The fabricated chip in 0.13μm CMOS demonstrates a sampling rate of 1-kS/s and a dynamic range of 117dB with a maximum conversion error of 0.32-percent while consuming only 11.3-μW from single supply voltage of 0.5V.