Analysis of gate dielectrics for SiC power UMOSFETS

It has been shown theoretically that the specific on-resistance of the drift region of SiC FETs is about 200 times lower than that of silicon FETs with the same breakdown voltage. However, it has been reported that the blocking performance of the UMOSFET is limited by the breakdown of the gate dielectric and not by avalanche breakdown in SiC. The analysis indicates that this is because the electric fields in the SiO/sub 2/, gate dielectric exceed the dielectric breakdown field strength when high voltages are being blocked by the UMOSFET, well before the electric fields in the SiC are high enough to cause avalanche breakdown in the semiconductor. This paper analyzes the impact of replacing SiO/sub 2/, with high dielectric constant gate insulators to solve this problem.