Analytical modeling of linearity and intermodulation distortion of 3D gate all around junctionless (GAA - JL) FET

Abstract This paper presents analytical modeling of linearity and intermodulation distortion of a rectangular GAA JL FET using 3D surface potential and drain current. The surface potential ( ψ ( x , y , z ) ) of the GAA JL FET is derived based on the ψ ( x , y , z ) dimension based approximation approach (i.e., weighted sum of ψ ( x , y ) and ψ ( x , z ) ). The proposed method provides an alternate solution that yields good accuracy, avoiding the critical mathematical computations of conventional 3D analysis. The depletion length and the drain current are also determined analytically. Moreover, with this current expression, the device's linearity performance has been examined based on P I P 3 , V I P 2 , V I P 3 , and I M D 3 . Therefore, the analysis optimizes the device's bias point for RFICs with an analytical model for better linearity performance.