Characterization Methodology for MOSFET Local Systematic Variability in Presence of Statistical Variability

In modern CMOS technologies, Local Layout Effects (LLE) induced by increased integration density translate into significant systematic variations of Logic delays. Accurate and test-efficient LLE characterization methodology of LLE is strongly required for supporting technology development decisions and for calibration of Design tools. Moreover, LLE impact tends to increase at low voltage operating conditions needed for Low Power applications. In this work, we study MOSFET electrical characterization methodology of systematic Local Layout Effects (LLE) met in 32 nm devices in presence of local random Statistical Variability (SV). MOSFET structures using Single Transistor (1T) and Multiple Parallel Transistors (MPT) are simulated with Monte-Carlo (MC) SPICE models in order to assess SV impact on DC characteristics; differences between 1T and MPT are analyzed, and MPT structures are shown to be better LLE sensors than 1T structures. By taking Well Proximity Effect (WPE) as LLE study case, we run experiments with MPT structures, and develop an analysis method to extract LLE signature from a limited set of 32 nm devices exposed to both Intradie SV and Interdie Process Variations (PV); the proposed MPT sensors and data analysis method are demonstrated as an accurate and test-efficient solution for characterization of LLE signatures in SV presence.