Safe operating area considerations in LDMOS transistors

The trade-off between breakdown voltage and on-resistance is a well-known feature of both lateral and vertical DMOS transistors. The trade-offs and restrictions imposed by the "safe operating area" are less familiar. The SOA defines limits on the excursion of the operating point in the I/sub d/-V/sub ds/ plane. To be correct, the SOA should also include thermal limitations; however, these can be treated separately. In this paper, we focus on the "electrical SOA", which is defined by a specific boundary line in the I/sub d/-V/sub ds/ plane. Although the LDMOS SOA has been discussed in a number of papers, the details of the device physics that determine the SOA boundary are still somewhat unclear and further work is needed. The main purpose of this paper is to investigate device behaviour in the neighborhood of the SOA boundary and then use these results to predict the SOA. We consider devices with and without drain extensions using a self-aligned body diffusion. The predicted SOA is shown to be in good agreement with measurements for both types of LDMOS. Current flow within the device is examined in detail. The observed SOA is shown to be consistent with the silicon power density limit, a fundamental characteristic of silicon devices. Finally, we show how a simplified two-terminal model of the drain region can be used to demonstrate the behaviour of the LDMOS as it approaches snap-back. This approach is analogous to that previously used to model the onset of avalanche initiated second breakdown in bipolar transistors (hower and Reddi, 1970).