Statistical link analysis of high-speed memory I/O interfaces during simultaneous switching events

Single-ended signaling systems, popular in memory I/O interfaces, are limited by signal and power integrity issues such as crosstalk and simultaneous switching output noise (SSO). At high data rates, the single-ended systems also suffers from random noise and timing jitter. In this paper, we present an integrated signal and power integrity simulation flow that combines statistical and transient simulation methods to enable the characterization of single-ended systems to account for random timing jitter in addition to the traditional SI issues focused on the deterministic noise such as intersymbol interference (ISI), crosstalk, and SSO noise. To include SSO noise, we co-simulate power distribution network (PDN) and channel models and treat SSO noise as another form of crosstalk. To capture any system nonlinearity, we employ time-domain based multi-edge response (MER) method to characterize the deterministic and passive portion of channels. Then, random noise and timing jitter impact are included via statistical approach. We use GDDR system to demonstrate our simulation flow.