3D-TV Rendering on a Multiprocessor System on a Chip

This thesis focuses on the issue of mapping 3D-TV rendering applications to a multiprocessor platform. The target platform aims to address tomorrow's multi-media consumer market. The prototype chip, called Wasabi, contains a set of TriMedia processors that communicate viaa shared memory, fast message passing channels that support multi-chip system and some application-specific co-processors. In the targeted market, it is important to verify that a system under design iscorrectly dimensioned. But during architecture research the applications for which the system is being designed are often not yet available. By mapping 3D-TV rendering applications to Wasabi, the performance figures are obtained not only to check the mapping feasibilitybut also to match the application requirements with the hardware architecture. In this thesis, two rendering algorithms are dealt withby following approach. First, sequential C code is developed. Thereafter, the code is optimized and vectorized using the special, SIMD-like media instructions supported by the TriMedia. Finally, multithreaded programs are developed and simulated on a cycle-accurate simulator of the Wasabi architecture to obtain the performance figures.