Test synthesis-cutting the Gordian Knot

The need to continually reduce the length of the design cycle has led to a rapid increase in the use of design automation tools. In particular logic synthesis, which allows a designer to specify a circuit at a high level using a language like VHDL has led to an increasing need to automate the test process. Logic synthesis assists in three areas of test: first, it removes redundant logic; second, it encourages designing in a synchronous fashion; and third, it allows mapping to inherently testable logic. By integrating design for test methodologies, such as scan path using tools like TransTEST, into the design process, logic synthesis tools, such as TransGATE, can be used to remove some of the overhead popularly associated with such technqiues, such as extra logic and tracking. This article is about the use of such tools to exploit the automatic insertion of test structures and the automatic generation of test vectors as a means of reducing the complexity of testing integrated circuits and replacing the error prone and less reliable non-integrated methods. >