Practical implications of via-middle Cu TSV-induced stress in a 28nm CMOS technology for Wide-IO logic-memory interconnect

The impact of isolated and arrayed 10×60µm via-middle Cu TSVs on 8LM 28nm node CMOS poly-SiON P/NFETs was electrically measured for proximities >4 µm at 27C and 105C. The largest observed shift in I on (<2.3%) is significantly less than that from other context-dependent sources such as dual stress liner boundaries (∼10%). NanoBeam Diffraction measurements of Si strain within 5µm of TSVs were acquired for samples prepared from fully processed wafers, showing that for proximity >1.5µm the impact of TSVs is negligible. Interaction with overlying interconnect is mitigated through optimization of post-TSV plating anneal to achieve <200A Cu pumping and by introducing a TSV unit cell designed to minimize the impact on local environment.