SOI SRAM/DRAM Cells for 0.5 V Operation

A four transistor static random access memory (4T SRAM) cell and a silicon-on-insulator dynamic random access memory (SOI DRAM) gain cell, both operating at low supply voltage, are proposed. Both cells actively exploit the body region of partially depleted SOI metal-oxide-semiconductor field-effect transistors (MOSFETs). The body region of an SOI MOSFET with an `H-shaped' gate electrode is used as a resistor in the inverter pair of the proposed SRAM cell. Its resistance is controlled independently from the threshold voltage of the main MOSFET. Simulation shows the stable operation of the proposed SRAM cell under a supply voltage of 0.5 V. The SOI DRAM gain cell consists of a p-channel junction field-effect transistor (JFET) and an n-channel MOSFET, where the source diffusion of the MOSFET functions as the gate diffusion of the JFET as well. Signal charge is stored in the gate diffusion capacitance of the JFET, leading to modulation in its source-drain conductance. Simulation also reveals that the proposed SOI DRAM gain cell operates properly under a supply voltage of 0.5 V.