A high-speed, high-linearity, and energy-efficient subranging single-side capacitor switching scheme for SAR ADCs

This paper presents a high-speed, high-linearity, and energy-efficient subranging single-side capacitor switching scheme for successive approximation register analog-to-digital converters. The presented capacitor switching scheme employs a subrange stage to resolve the first few bits, which are adopted by the proposed single-side-based detect-and-skip switching algorithm in the main stage. Compared with conventional architecture, the proposed switching algorithm achieves a 98.0% less switching energy, a 72.5% smaller area, a 38.1% faster comparison process, and a 38.4% less comparator energy consumption.