A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry

A soft-error-immune, 0.9-ns address access time, 2.0-ns read/write cycle time, 1.15-Mb emitter coupled logic (ECL)-CMOS SRAM with 30-ps 120 k ECL and CMOS logic gates has been developed using 0.3-/spl mu/m BiCMOS technology. Four key developments ensuring good testability, reliability, and stability are on-chip test circuitry for precise measurement of access time and for multibit parallel testing, a memory-cell test technique for an ECL-CMOS SRAM, a highly stable current source with a simple design using a current mirror, and a soft-error-immune memory cell using a silicon-on-insulator (SOI) wafer. These techniques will be especially useful for making the ultrahigh-speed, high-density SRAM's used as cache and control storages in mainframe computers.