A Digital Background Calibration Algorithm of Pipelined ADC Based on Pesudo-Random Sequence

A digital background calibration algorithm of pipelined ADC based on pseudo-random sequence is presented. Errors caused by gain error and nonlinearity are corrected to improve the performance of ADC. Capacitor mismatch are simultaneously calibrated to improve the linearity without extra circuit. Behavioral simulation of a 12bit pipelined ADC has been performed with a sampling rate of 160MHz and an input rate of 1.00586MHz. Results show this calibration algorithm improve SFDR from 59.8dB to 93.9dB, SNDR from 50.1dB to 73.1dB and ENOB from 8.0bit to 11.9bit.