Wafer Level Reliability Characterization of 2.5D IC packages

Via-Last TSV based 2.5D/3D IC packaging is actively being pursued for its ability to extend Moore’s law beyond the limitations inherent in 2D packaging, though challenges for optimizing electrical test continue to be addressed. This paper discusses a wafer level testable design approach that eliminates the need to probe wafer on substrate bumps and carries the advantage of performing reliability tests at wafer level. A number of design, assembly, electrical and reliability test considerations are detailed.