Impact of Epi-Si growth temperature on Ge-pFET performance

In this study, we report a direct comparison between two Epitaxial silicon processes: 500°C using SiH 4 and 350°C using Si 3 H 8 . Following four different metrics, we demonstrate that the reduction of Silicon growth temperature results into the introduction of negatively charged defects possibly located at the Si/SiO 2 interface. However, the Epi Si growth at 350°C with Si 3 H 8 remains beneficial compared to a growth performed at 500°C-SiH 4 especially when thin EOT Ge pFETs are targeted.