A Novel Built-in Aging Detection Architecture for Mixed-Signal Integrated Circuits

Electronic systems such as used in automotive or industrial applications require highly reliable micro-electronic systems, especially ASICs. This paper presents a novel built-in aging detection architecture which monitors the degradation of the digital and analog circuit in operation so as to achieve triggering of a failure warning a certain time distance ahead of the wear-out region of an IC. The proposed program-able guardband interval and stability checker in aging monitor provides various prediction levels of aging time step and also more resilient detection on temperature, supply voltage and process variations. Simulation results are presented using a 0.15??m CMOS standard process and show that the new on-line failure prediction circuit is very useful for safety or mission critical applications. Index Terms ? circuit reliability, mixed-signal, delay monitor, aging sensor