GENETIC ALGORITHM BASED ROUTERS ARRANGEMENT IN NETWORK ON CHIP USING THE UNION MULTIPROCESSOR

System On Chip is a complete integrated system because it consists of several different microprocessor subsystems together with memories and I/O interfaces. So the connection between these IP’s components are the major issue and the Network On Chip (NOC) plays an important role in connecting these IP’s. The adaptive XY routing never runs into deadlock or live lock therefore it consumes more power and it also passes the data through fault path. In the proposed, a new Network On Chip use Genetic Algorithm which is an optimization algorithm used to find the shortest path and critical path analysis by routing the router on four sides so this algorithm is free from live lock and deadlock problem thereby it consumes less power. It also finds fault part of NOC components by using fault analysis process to identify the damaged router in NOC chip architecture. The experimental results shows reduction in power with 20% and delay can be reduced with 40% on average compared to adaptive router architecture for network on chip.