Reliability issues of offset drain transistors after different modes of static electrical stress

Abstract The reliability issues of Offset Drain Transistors (ODT's) after different modes of static electrical stress (high voltage uniform gate stress, high voltage drain stress and hot carrier stress) are presented. Besides, the evolution of the macroscopic electrical parameters of these devices after high voltage uniform gate stress, has been attributed quantitatively to the evolution of the bulk gate oxide trapping characteristics and the variation of the Si/SiO 2 interface state charge. Furthermore, qualification of these devices for application in non-volatile memory arrays as bit select transistor has been conducted.