Coherence and synchronization mechanism to channel controllers e / s in a data processing system.

CONTROLLER CHANNEL INPUT / OUTPUT IMPLEMENT MECHANISMS OF CONSISTENCY AND TIMING THAT ALLOW THE DRIVER CHANNELS INPUT / OUTPUT PROVIDE OPERATIONS REPORT OF FULLY CONSISTENT ACCESSIBLE IN A BUS SYSTEM multiprocessor WITHOUT IMPLEMENT THE PROTOCOL RETRY. THIS IS POSSIBLE TO MAKE THE CACHE DELAYED invalidating CONFLICTS OF CONSISTENCY OF CACHE OF REAL TIME BETWEEN PROCESSORS AND DEVICES INPUT / OUTPUT. IN ADDITION, THE DMA WRITING IN / OUT REAL TIME TO OCCUR IN MEMORY SYSTEM AND WITHOUT READING WITH TRADITIONAL OPERATIONS intention to modify (RWITM). TERMINATION OF OPERATIONS PIO WAS ASSOCIATED WITH THE TERMINATION OF OPERATIONS OF WRITING DMA INPUT / OUTPUT TIMING TO PROVIDE INPUT / OUTPUT smoothly TO THE OPERATION OF THE PROCESSOR. IOCC DESCRIBED AN IMPLEMENTATION BENEFITING FROM THOSE TECHNIQUES TO REDUCE COMPLEXITY DELDISENO SIGNIFICANTLY.