Analog encoded neural network for power management in MPSoC

Encoded neural networks mix the principles of associative memories and error-correcting decoders. This paper introduces an analog implementation of this new type of network to manage the power distribution in Multiprocessor System-on-Chip (MPSoC). The proposed circuit has been designed for the 1V supply ST CMOS 65nm process, with a low complexity and low power consumption (less than 1% of the MPSoC power). Compared to a digital counterpart based on game theory, this analog solution consumes 6800 times less energy and reacts 4500 times faster. Thus, this analog circuit allows to fully exploiting DVFS circuits switching capabilities to continuously adapt the power distribution of an MPSoC.