In this paper, Al fluoride defects on microchip Al bondpads were studied, which were confirmed to be due to a 12 hours delay prior to NE111 clean process. Failure analysis results and mechanism were discussed. Moreover, a preventive solution of introducing a time link between passivation etch and NE111 clean process was recommended and implemented
To identify nitride from oxide layer on the trench, it is necessary to perform BOE chemical staining. However, chemical staining using BOE will damage the oxide layer, causing inaccurate readings in the oxide gauging measurement in the trench. Moreover, damage on the oxide layer caused heavy charging at the side of the trench and the surface of oxide layer. In this paper, we proposed to coat a Cr layer over the trench before chemical staining. The damage problem was eliminated and the measurement of oxide gauging was more accurate. A application case is discussed for trench TEOS gauging measurement.
Abstract After wafer-die sawing process, sometimes silicon (Si) dust on microchip Al bondpads is difficult to be cleaned away by DI water, especially at pinhole/corrosive areas caused by galvanic corrosion, thus resulting in non-stick on pads (NSOP) problem in assembly process. To eliminate NSOP problem due to Si dust contamination, in this paper, we will study the mechanism of Si dust contamination and propose a concept of Si dust corrosion. A theoretical model will be introduced so as to explain Si dust contamination and corrosion problem during wafer die sawing process. Based on the mechanism proposed, Si dust contamination and corrosion is related to galvanic corrosion as OH- ions generated from galvanic corrosion will not only react with Al to cause Al corrosion, but also react with Si dust to cause Si dust corrosion. During Si dust corrosion, poly-H2SiO3 and Si-Al-O complex compounds will be formed on Al bondpads, especially at the pinholes/corrosive areas. Poly-H2SiO3 and Si-Al-O complex compounds are “gel-like” material and stick onto the surface of bondpads. It is insoluble in water and difficult to be cleaned away by DI water during or after wafer die sawing process and will cause bondpad discoloration or/and NSOP problem. Some eliminating methods of Si dust contamination and corrosion on Al bondpads during wafer die sawing process are also discussed.
In this paper, an ET high Via resistance case as investigated. TEM/EDX technique was used for identification of the root cause. Failure mechanism of Al fluoride defects is discussed. Some preventive actions/solutions were implemented to improve the process margin and eliminate the problem.
In this paper few case studies of Auger elemental analysis in failure analysis of wafer fabrication, using a state-of-the-art scanning Auger nanoprobe, will be presented. Material identification in particle defects is quite challenging especially in advanced microelectronic technologies, 90nm and beyond, where, due to decreasing device size, the tight pitch and high aspect ratio of features introduces constraints of analysis. Thus, the case studies discussed in the paper are all pertaining to the front-end related defects, at poly+contact region of the die, where these contraints are expected to be severe. It will be shown that the scanning Auger nanoprobe can be used for the elemental analysis of features as small as 10nm.
Airborne boron and phosphorus contaminations on wafer surface has been analysed by TOF-SIMS. A known boron and phosphorus concentration BPSG sample was used as reference for the calibration of the TOF-SIMS. The detection limit reaches 1E8 at/cm2 for boron and 1E10 at/cm2 for phosphorus. This method is easy to applied and no sample preparation required. So TOF-SIMS is a very good monitoring technique for airborne boron and phosphorus on wafer surface.
In this paper, an FIB method using progressive multi-cut technique is proposed and it has been applied in failure analysis of wafer fabrication. The application results showed that this method would greatly improve FIB cut success rate, especially for invisible defects. A case study on Vbd ramp up failure after QBD short loop will be presented.
Abstract Galvanic corrosion (two metal corrosion) on microchip Al bondpads may result in discolored or non-stick bondpad problem. In this paper, a galvanic corrosion case at bondpad edge will be presented. Besides galvanic corrosion (Al-Cu cell), a concept of galvanic corrosion (Al-Ti cell) is proposed, which is used to explain galvanic corrosion at bondpad edge with layers of TiN/Ti/Al metallization structure. A theoretical model of galvanic corrosion (Al-Ti cell) is proposed to explain chemically & physically failure mechanism of galvanic corrosion at bondpad edge. According to the theoretical model proposed in this paper, galvanic corrosion on microchip Al bondpads could be identified into two corrosion models: galvanic corrosion (Al-Cu cell) occurred mostly at the bondpad center and galvanic corrosion (Al-Ti cell) occurred specially at bondpad edge with TiN/Ti/Al metallization structure. In this paper, a theoretical model of galvanic corrosion (Ai-Ti cell) will be detail discussed so as to fully understand failure mechanism of galvanic corrosion the bondpad edge. Moreover possible solutions to eliminate galvanic corrosion (Al-Ti cell) are also discussed.
Energy-dispersive X-ray microanalysis technique has been commonly used in failure analysis. It is vital for an analyst to understand the electron penetration depth in a certain material so as to be able to select an appropriate accelerating beam voltage. In this paper, we will use the Monte Carlo electron flight simulation method to obtain the electron penetration data at the different beam acceleration voltages of 5kV, 10kV, 15kV, 20kV, 25kV and 30 kV for the various possible elements/materials in wafer fabrication.
This paper presents the effects of Auger electron spectroscopy on semiconductor device's threshold voltage performance. Bond pads connected to gate of transistors were exposed to different beam energy of 0, 3, 5, 10, 15 and 20 keV for an average of 2.5 minutes. Vt measurements were collected once at pre-exposure and thrice at post-exposure. The evaluation results show that the transistor Vt was impacted and shifted after exposure to electron beam at varying energy levels (3, 5,10, 15 and 20 keV) during AES analysis.
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