Studies on Failure Mechanism of ET High Via Resistance in Wafer Fabrication
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In this paper, an ET high Via resistance case as investigated. TEM/EDX technique was used for identification of the root cause. Failure mechanism of Al fluoride defects is discussed. Some preventive actions/solutions were implemented to improve the process margin and eliminate the problem.Keywords:
Failure mechanism
Wafer fabrication
Identification
Abstract Fault isolation is the most important step for Failure Analysis (FA), and it is closely linked with the success rate of failure mechanism finding. In this paper, we will introduce a case that hard to debug with traditional FA skills. In order to find out its root cause, several advanced techniques such as layout tracing, circuit edit and Infrared Ray–Optical Beam Induced Resistance Change (IR-OBIRCH) analysis had been applied. The circuit edit was performed following layout tracing for depositing probing pads by Focused Ion Beam (FIB). Then, IR-OBIRCH analysis with biasing on the two FIB deposited probing pads and a failure location was detected. Finally, the root cause of inter- metal layer bridge was found in subsequent physical failure analysis.
Root Cause Analysis
Fuse (electrical)
Failure mechanism
Tracing
Biasing
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The success of the electrical fault isolation will assist in narrowing down to the most possible fault location with confidence, and thus increase the success rate in determining the failure mechanism during physical failure analysis. However, any form of recovery from the failure could result in inability to determine the root cause. For example, they are either the sample unable to send to FA since the device is passing, or unable to continue the fault isolation since recovery occurred during analysis. This technical paper will discuss on the investigation of recovery symptom in scan related failure for 55nm wafer technology devices. Through study and investigation, recovery avoidance is implemented during testing, and a new stress flow is identified to reactivate the failure mode. Thus, recoverable failure mechanism like passivation crack and metal defects are identified. The learning from the recovery characteristics also help to forecast possible failure mechanism based on the scan diagnostics and electrical fault isolation findings.
Failure mechanism
Failure causes
Isolation
Catastrophic failure
Passivation
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As the design of integrated circuits has become increasingly complicated and dense, serious wafer quality problems are observed in modern wafer fabrication facilities. Therefore, in cluster tools of leading fabs process chambers are periodically cleaned in order to eliminate residual chemicals and impurities that can damage the wafer quality. A chamber cleaning operation is mainly applied to tools in which a wafer delay has a crucial impact on the wafer quality, and hence the need of wafer delay control becomes more significant when chamber cleaning is considered. Thus, we first examine how wafer delays can be specified for cluster tools with chamber cleaning operations. We confirm that wafer delays are substantially increased when chambers are periodically cleaned, and we show that such increased wafer delays cannot be eliminated or reduced using the existing scheduling methods. In such a case, we prove that a partial loading strategy can minimise both the tool cycle time and the wafer delays by controlling the number of wafers being loaded into parallel chambers. We also present how wafer delays under the partial loading strategy can be further reduced by introducing a timing control method that regulates the start times of robot tasks.
Wafer fabrication
Wafer-scale integration
Wafer backgrinding
Wafer-level packaging
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We have estimated the problems of high energy application to memory device fabrication from the point of wafer crystalline structure. Following a series of experiments, we have found the different implantation damage induced by the variations of off-cut and azimuth angle of wafer and show that the difference can be reduced if the tilted wafer is adopted. The use of off-angle wafer also minimizes the shadowing effect depending on the tilt angle of implantation because there is no need to use the tilting method in ion implantation process.
Wafer fabrication
Wafer Bonding
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Abstract Finding the real root cause of electrically damaged devices is often challenging where it can mask out the real failure mechanism. The electrical damages might (might probably, one doubtful word is enough) be a consequence of the real failure mechanism. This paper aims to present cases and techniques to overcome the challenges of electrically damaged devices in identifying the real failure mechanism.
Failure mechanism
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Wafer fabrication
Semiconductor device fabrication
Wafer backgrinding
Semiconductor device modeling
Die preparation
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Abstract It is well-known that underetch material, contamination, particle, pinholes and corrosion-induced defects on microchip Al bondpads will cause non-stick on pads (NSOP) issues. In this paper, the authors will further study NSOP problem and introduce one more NSOP failure mechanism due to Cu diffusion caused by poor Ta barrier metal. Based on our failure analysis results, the NSOP issue was not due to the assembly process, but due to the wafer fabrication. The failure mechanism might be that the barrier metal Ta was with pinholes, which caused Cu diffused out to the top Al layer, and then formed the “Bump-like” Cu defects and resulted in NSOP on Al bondpads during assembly process.
Failure mechanism
Root Cause Analysis
Barrier layer
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Background: Standard patterned sample with programed defects (PDs) is effective to evaluate the tool performance of pattern inspection system, but the fabrication of such standard sample, having large area dense patterns with PDs suitable for the evaluation of sub-7-nm node, is difficult. Aim: The goal of this study is to fabricate a standard sample to evaluate the performance of inspection tool for below 7-nm nodes. Approach: We use electron beam lithography with an acceleration voltage of 130 keV to fabricate standard sample. Results: We form large area dense sub-16-nm half pitch (hp) line and space (LS) patterns with PDs on 300-mm-Si-wafers, and 10- to 7-nm hp LS patterns on a 100-mm-Si wafer. Approximately 5-nm PDs with shapes including protrusions, intrusions, bridges, and openings are formed without additional defects. Moreover, pattern-etched Si wafers with 16- to 12-nm hp LS are successfully fabricated. A 100-mm-wafer with patterns is mounted into a 300-mm-Si wafer. Conclusions: The acceleration voltage of 130 keV is sufficient for the fabrication of large area dense pattern with PDs suitable for the evaluation of sub-7-nm node. Moreover, the fabricated standard wafers are useful to evaluate the tool performance of the inspection system for 300-mm wafer fabrication.
Wafer fabrication
Die preparation
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Root Cause Analysis
Failure causes
Failure mechanism
Mode (computer interface)
Component (thermodynamics)
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In this paper we point out that the application of standard SPC charts for process control during wafer fabrication could lead to errors due to the presence of the lot-to-lot and wafer-to-wafer variations. We illustrate that the error could increase the "lots-at-risk" by as much as 17%. We present a new SPC model which accounts for the lot-to-lot and wafer-to-wafer variations. Then, we present an adaptive sequential two-lot control policy, where we sample the successive lot when there is an out-of-control signal, and investigate for the process shift only when the successive lot also gives an out-of-control signal. This adaptive method outperforms the static policy as long as the lot-to-lot variance is smaller than the wafer-to-wafer variance. However, when the wafer-to-wafer variance is higher than the lot-to-lot variance, the information from a successive lot is less variance than the information from additional wafers in the same lot.
Wafer fabrication
Wafer backgrinding
SIGNAL (programming language)
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