Rat lymphoid cells, TARS-1, immortalized by coculture with adult T-cell leukemia cells, were intraperitoneally injected into 65 newborn, inbred WKAH/Hkm rats. In most of the rats, tumor nodules were discernible 7 to 15 days after transplantation but were completely rejected within 5 to 6 weeks. Two rats with no tumor nodules exhibited gait disturbances and paralysis of the hind legs 3 to 4 weeks after transplantation. Histological and hematological examinations revealed that a lymphoma/leukemia-like disease had developed in one of the two rats, and the T-lymphoid cell line WLeuk-1 was established from peripheral blood mononuclear cells from this rat. When the WLeuk-1 cells were transplanted into newborn WKAH/Hkm rats, the animals died of a lymphoma/leukemia-like disease within several weeks after transplantation, in contrast to their rejection of the TARS-1 cells. Southern blot and karyotype analyses revealed that WLeuk-1 cells had retained the marker chromosomes and human T-lymphotropic virus type I (HTLV-I) integration patterns of the parent cell line, TARS-1. The additional specific chromosome abnormalities 3p+,t (12;13), and Xq+ were found in the WLeuk-1 cells. Moreover, the expression of HTLV-I structural proteins was slightly depressed in WLeuk-1 cells, while that of the transacting factors p40tax and p21x, but not that of p27rex, was enhanced about fivefold compared with that in TARS-1. The transactivating function of p40tax was intact in WLeuk-1, as evidenced by enhanced interleukin-2 receptor alpha chain expression. These results suggest that aberrant expression of HTLV-I regulatory genes and alteration of cellular genes were associated with the phenotypic progression of the WLeuk-1 cell line.
Although limits of down-scaling of Si-CMOS FETs have been argued for many years, the down-scaling is the most realistic and effective way for the moment to decrease power consumption, increase performance, and also decrease the cost for massproduced integrated circuits, and thus, the CMOS down-scaling competition has heated-up among major semiconductor companies and their alliances. Because of its nature of effectively suppressing the off leakage current with gate around configuration, the Si nanowire FET has been thought be the ultimate structure for ultrasmall CMOS devices towards their downsizing limit. Recently, several experimental data of Si nanowire FETs with very high oncurrent much larger than that of planar MOSFETs have been published. Thus, Si nanowire FETs are now drawing attention as the most promising candidate for the mainstream CMOS devices in 2020s. In this paper, recent research status of Si nanowire FETs in experimental and theoretical works are described.