Extreme ultraviolet lithography (EUVL) is the most promising candidate for the manufacture of devices with a half pitch of 32 nm and beyond. We are now evaluating the process liability of EUVL in view of the current status of lithography technology development. In a previous study, we demonstrated the feasibility of manufacturing 32-nm-node devices by means of a wafer process that employed the EUV1, a full-field step-and-scan exposure tool. To evaluate yield, a test pattern was drawn on a multilayer resist and exposed. After development, the pattern was replicated in SiO2 film by etching, and metal wires were formed by a damascene process. Resolution enhancement is needed to advance to the 22- nm node and beyond, and a practical solution is off-axis illumination (OAI). This paper presents the results of a study on yield improvement that used a 32-nm-node test chip, and also clarifies a critical issue in the use of EUVL in a wafer process for device manufacture at the 22-nm node and beyond.
A strategy of resist design for the resolution limit of KrF imaging is investigated, and then the possibility of 130 nm lithography using KrF imaging is discussed. An extremely thin resist in a thickness of less than 150 nm was developed for KrF imaging at the resolution limit. The resist could overcome crucial problems of nanoedge roughness as well as degraded resist profiles without sacrificing resolution capability even when reducing the resist thickness to extreme limits. Moreover, a resist thickness of 80 nm could narrowly perform 130 nm lithography using an unconventional KrF imaging system featuring a numerical aperture of 0.6 and a partial coherency of 0.75 with 2/3 annular aperture, without using any phase shift mask technologies.
We investigated dependence of ArF resist on Exposed Area Ratio (EAR). Because it can be one of the CD variation factor and it is difficult to correct by OPC. Acrylate polymer based resist showed dependence on EAR. At low EAR, resist showed T-top profile and its CD became large. It could be considered that the profile change was caused by acid evaporation and re-sticking. Resist profile simulation indicated that CD variation appeared at only low EAR. To decreasing the effect of acid evaporation and re-sticking, we tried to increase the amount of acid evaporation by increasing PAB temperature. CD variation by EAR was decreased with increasing PAB temperature.
An Illumination intensity distribution of an exposure tool varies CD in simulation. In order to obtain reliable resist parameters, we studied the influence of the illumination intensity distribution in tuning the resist parameters and the accuracy of the simulation using the tuned resist parameters under different illumination conditions from in tuning. We tuned resist parameters with two models of illumination intensity to experimental FEM data. One model, "Nominal", was assumed to be uniform intensity and a nominal shape of an exposure tool. Another model, "Measured", was measured illumination intensity distribution with grating-pinhole mask. Under the same illumination condition to tuning, RMS of CD difference between experiment and simulation using "Measured" in tuning and simulation was 0.7nm smaller than that using "Nominal". But under the different illumination condition from tuning, RMS using "Measured" was 1.4 - 1.6nm smaller in total of 1D-pattern than that using "Nominal". In the specific pattern RMS using "Measured" was rather smaller than RMS using "Nominal". These results indicate that, in order to gain accurate simulation result, the accurate illumination intensity distributions is need in tuning and simulation. If using "Nominal" in tuning and in simulation, CD difference between experiment and simulation will enlarge in fine patterns.
This paper concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacture based on accelerated development in critical areas and the construction of a process liability (PL) test site that integrates results in these areas. The overall lithography performance was determined from the performance of the exposure tool, the printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 mm × 33 mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. Thus, the test site was designed for the full-field exposure of various pattern sizes [half-pitch (hp) 32-50 nm]. The CD variation of the mask was found to be as good as 2.8 nm (3σ); and only one printable defect was detected. The effect of flare on CD variation is a critical issue in EUVL; so flare was compensated for based on the point spread function for the projection optics of the EUV1 and aerial simulations that took resist blur into account. The accuracy obtained when an electronic design automation (EDA) tool was used for mask resizing was found to be very good (error ≤ ±2 nm). Metal wiring patterns with a size of hp 32 nm were successfully formed by wafer processing. The production readiness of EUVL based on the integration of results in these areas was evaluated by electrical tests on low-resistance tungsten wiring. The yield for the electrically open test for hp 50 nm (32-nm logic node) and hp 40 nm (22-nm logic node) were found to be over 60% and around 50%, respectively; and the yield tended to decrease as patterns became smaller. We found the PL test site to be very useful for determining where further improvements need to be made and for evaluating the production readiness of EUVL.
Current status of EUV resists including imaging performance and resist out-gassing were described. As a result of resist benchmarking using small field exposure tool that has stand alone EUV source and 0.3 numerical aperture projection optics, resolution limit of 25nm was obtained in certain resist material. This is potential candidate for below 32nm node devices fabrication. On the other hand, sensitivity of 20-30mJ/cm2 and line width roughness of 4-7nm should be improved. Moreover, as a result of resist out-gassing analysis using originally designed out-gassing evaluation tool, the resist out-gassing was not large for initial exposure tool, but it should be minimized for volume manufacturing exposure tool. In the near future, completely new resist material and/or new resist processing are strongly expected. Furthermore fundamental research such as understanding reaction mechanism of resist pattern formation and synthesis of new resin and photo-acid generator are still needed to realize 22nm node device manufacturing.
A 70 nm pitch two-level interconnects have been successfully fabricated using extreme ultraviolet lithography (EUVL) (λ=13.5 nm). EUVL enabled us to obtain fine pattern formation and usable overlay accuracy at each metal and via patterning. CF 3 I etching gas and ruthenium (Ru) barrier film deposited with physical vapor deposition (PVD) are key technologies for achieving good electrical properties. Very low effective resistivity of less than 4.5 µΩ cm in 35-nm-width wiring was obtained by using PVD-Ru barrier film. Via resistance of 12.4 Ω for via-holes with diameter of 35 nm was obtained.
