A novel LDMOS featuring bulk full gate (BFG) with bulk channel and electron accumulation effect, named BFG-LDMOS, is proposed and investigated. The BFG includes bulk gate oxide (BGO) that is inserted in the ${N}$ -drift and the full gate (FG) that is formed by the wide open base transistor (P-body/ ${N}$ -drift/P + ). The gate potential is extended in the gate- ${N}$ -drift-drain (GND) region, and thus, the bulk channel of the P-body and electron accumulation effect of the ${N}$ -drift in the source- ${N}$ -drift-drain (SND) region is achieved, which significantly reduces the specific ON-resistance ( ${R}_{\text {ON,sp}}$ ). In addition, the P-body, ${N}$ -drift, and N + drain are divided by the BGO, and the P-body/ ${N}$ -drift junction (PN1) sustains the breakdown electric field for both sides, which guarantees the breakdown voltage (BV) like conventional LDMOS. The 3-D simulation results indicate that the BV and ${R}_{\text {ON,sp}}$ are 249 V and 2.93 $\text{m}\Omega \cdot $ cm 2 for the proposed BFG-LDMOS, respectively, and the Baliga's figure of merit (FoM) is high up to 21 MW/cm 2 , which breaks through the silicon limit of the reduced surface field (RESURF).
A novel snapback-free and fast-switching Shorted-Anode Lateral Insulated Gate Transistor (SA LIGBT) with Multiple Current P-Plugs (MCP) in anode, named MCP LIGBT, is proposed and investigated. The device features Multiple separated Current P-Plugs which are inserted in the N-buffer. At the forward conduction mode, the MCP act as the potential barrier to block the electrons flowing directly to the N+ anode, and the N-channels sandwiched between the MCP are fully depleted, which both increase the anode distributed resistance (RSA). In the turn off process, the N-channels provide three high-speed paths for minorities extraction, which reduces the turn off time. Consequently, the proposed device not only eliminates the snapback effect, but also achieves superior tradeoff between Eoff and Von. At the same Von of 1.6 V, it reduces the Eoff by 45%, 22%, and 14% compared with the VPN LIGBT, SSA LIGBT and NCA LIGBT, respectively. Meanwhile, it exhibits the lowest Von of 1.21 V at Eoff of 2 mJ/cm2.
Abstract All‐inorganic semiconductor perovskite quantum dots (QDs) with outstanding optoelectronic properties have already been extensively investigated and implemented in various applications. However, great challenges exist for the fabrication of nanodevices including toxicity, fast anion‐exchange reactions, and unsatisfactory stability. Here, the ultrathin, core–shell structured SiO 2 coated Mn 2+ doped CsPbX 3 (X = Br, Cl) QDs are prepared via one facile reverse microemulsion method at room temperature. By incorporation of a multibranched capping ligand of trioctylphosphine oxide, it is found that the breakage of the CsPbMnX 3 core QDs contributed from the hydrolysis of silane could be effectively blocked. The thickness of silica shell can be well‐controlled within 2 nm, which gives the CsPbMnX 3 @SiO 2 QDs a high quantum yield of 50.5% and improves thermostability and water resistance. Moreover, the mixture of CsPbBr 3 QDs with green emission and CsPbMnX 3 @SiO 2 QDs with yellow emission presents no ion exchange effect and provides white light emission. As a result, a white light‐emitting diode (LED) is successfully prepared by the combination of a blue on‐chip LED device and the above perovskite mixture. The as‐prepared white LED displays a high luminous efficiency of 68.4 lm W −1 and a high color‐rendering index of Ra = 91, demonstrating their broad future applications in solid‐state lighting fields.
A novel super-junction LDMOS with low resistance channel (LRC), named LRC-LDMOS based on the silicon-on-insulator (SOI) technology is proposed. The LRC is highly doped on the surface of the drift region, which can significantly reduce the specific on resistance ( R on,sp ) in forward conduction. The charge compensation between the LRC, N-pillar, and P-pillar of the super-junction are adjusted to satisfy the charge balance, which can completely deplete the whole drift, thus the breakdown voltage ( BV ) is enhanced in reverse blocking. The three-dimensional (3D) simulation results show that the BV and R on,sp of the device can reach 253 V and 15.5 mΩ ⋅ cm 2 , respectively, and the Baliga’s figure of merit ( FOM = BV 2 / R on,sp ) of 4.1 MW/cm 2 is achieved, breaking through the silicon limit.
Abstract This paper presents a comprehensive analysis of the short-circuit failure mechanisms in commercial 1.2 kV planar silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) under 400 and 800 V bus voltage conditions. The study compares two products with varying short-circuit tolerances, scrutinizing their external characteristics and intrinsic factors that influence their short-circuit endurance. Experimental and numerical analyses reveal that at 400 V, the differential thermal expansion between the source metal and the dielectric leads to cracking, which in turn facilitates the infiltration of liquid metal and results in a gate–source short circuit. At 800 V, the failure mechanism is markedly different, attributed to the thermal carrier effect leading to the degradation of the gate oxide, which impedes the device's capacity to switch off, thereby triggering thermal runaway. The paper proposes strategies to augment the short-circuit robustness of SiC MOSFETs at both voltage levels, with the objective of fortifying the device's resistance to such failures.
A novel shorted anode lateral-insulated gate bipolar transistor (SA LIGBT) with snapback-free characteristic is proposed and investigated. The device features a controlled barrier V barrier and resistance R SA in anode, named CBR LIGBT. The electron barrier is formed by the P-float/N-buffer junction, while the anode resistance includes the polysilicon layer and N-float. At forward conduction stage, the V barrier and R SA can be increased by adjusting the doping of the P-float and polysilicon layer, respectively, which can suppress the unipolar mode to eliminate the snapback. At turn-off stage, the low-resistance extraction path (N-buffer/P-float/polysilicon layer/N-float) can quickly extract the electrons in the N-drift, which can effectively accelerate the turn-off speed of the device. The simulation results show that at the same V on of 1.3 V, the E off of the CBR LIGBT is reduced by 85%, 73%, and 59.6% compared with the SSA LIGBT, conventional LIGBT, and TSA LIGBT, respectively. Additionally, at the same E off of 1.5 mJ/cm 2 , the CBR LIGBT achieves the lowest V on of 1.1 V compared with the other LIGBTs.
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