A super-junction SOI-LDMOS with low resistance electron channel
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A novel super-junction LDMOS with low resistance channel (LRC), named LRC-LDMOS based on the silicon-on-insulator (SOI) technology is proposed. The LRC is highly doped on the surface of the drift region, which can significantly reduce the specific on resistance ( R on,sp ) in forward conduction. The charge compensation between the LRC, N-pillar, and P-pillar of the super-junction are adjusted to satisfy the charge balance, which can completely deplete the whole drift, thus the breakdown voltage ( BV ) is enhanced in reverse blocking. The three-dimensional (3D) simulation results show that the BV and R on,sp of the device can reach 253 V and 15.5 mΩ ⋅ cm 2 , respectively, and the Baliga’s figure of merit ( FOM = BV 2 / R on,sp ) of 4.1 MW/cm 2 is achieved, breaking through the silicon limit.Keywords:
LDMOS
Pillar
Figure of Merit
The floating-body effect and impact ionization generate excess holes that are amplified by the parasitic bipolar junction transistor (BJT) in silicon-on-insulator lateral double-diffused MOSFETs (SOI-LDMOS) that degrade the transistor performance. In this paper, a novel silicon germanium (SiGe) window LDMOS on SOI (SW-SOI) is reported where the buried oxide under the channel region becomes thinner and a SiGe window has been replaced in order to reduce the hole concentration in the channel and control the BJT effect significantly. The novel features of an SW-SOI are simulated and compared with a conventional LDMOS on SOI (C-SOI). In addition, reduced self-heating effects and higher breakdown voltage have been achieved as compared with the C-SOI. Hence, this paper illustrates the benefits of the high performance SW-SOI device over a conventional one and expands the application of SOI MOSFETs to high temperature.
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Impact ionization
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The P-sink structure is widely used in silicon-on-insulator (SOI) power devices (SOI-LIGBT and SOI-LDMOS) to extend the electrical safe operating area (E-SOA) as it can suppress the trigger of the parasitic transistor. In this paper, the electrical behavior and reliability issues in the extended E-SOA for 200-V SOI power devices with P-sink structures are investigated for the first time. For SOI-LIGBT, the normal I - V curve and small hot-carrier-induced degradation are observed in the extended E-SOA; thereby, the P-sink structure plays a good role. However, for SOI-LDMOS, two mechanisms dominate the electrical behavior in the extended E-SOA so as to bring the unusual “hump” in the I - V curve; meanwhile, it results in serious hot-carrier-induced degradation, reducing the lifetime of the device in practical applications. As a result, the P-sink structure is not the best choice to extend the E-SOA of SOI-LDMOS.
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Insulated-gate bipolar transistor
Sink (geography)
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Degradation
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We analytically and numerically investigate the performance of Laterally-Diffused Metal-Oxide-Semiconductor (LDMOS) transistors with Semi-circular Field OXide (S-FOX) focusing on mid-voltage (30 V – 100 V) power applications. We derive an analytical relation between breakdown voltage and on-resistance to realize the ideal behavior of the drift region for an LDMOS with S-FOX. Then, we find the optimized drift doping concentration minimizing the on-resistance at a given breakdown voltage. We introduce a new figure-of-merit for the drift region of a lateral device with S-FOX. We finally verify our ideal analytical findings with numerical results modeled and simulated in a commercial Technology Computer-Aided Design (TCAD).
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Power MOSFET
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In this paper, a novel 4H-SiC double reduced surface field (RESURF) LDMOS with a one-step doped Ptop layer and a Pburried layer (SDP LDMOS) has been proposed to optimize the electric field distribution and enhance the breakdown voltage. By using the step doping (SD) technology, the Ptop layer and the Pburried layer introduced extra electric field peaks in the drift region, hence the lateral and the vertical electric field distributions have been optimized simultaneously and the breakdown voltage has been improved significantly. In addition, the Pburried layer facilitated the depletion of the drift region. Therefore, for similar breakdown voltage rating, higher doping concentration of the drift region and smaller specific on-resistance have been achieved. It was found by the finite element numeric simulation that the proposed device exhibited a high breakdown voltage (BV) of 1934 V and a low specific on-resistance (Ron,sp) of 4.04 mΩ·cm 2 (at V GS = 10 V, V DS = 1 V), resulting in a 49% higher Baliga's figure of merit (FOM, defined as BV 2 /Ron,sp) 925.8 MW/cm 2 than that of the conventional double RESURF LDMOS.
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Silicon-on-insulator (SOI) LDMOS transistors with a linearly graded doping profile in the drift region have been found to exhibit both low on-resistance and high breakdown voltage. High-side operation is a problem for devices built in very thin SOI layers due to pinch-off of the drift region. This is less of a problem for devices built in thicker SOI layers. Devices built in thicker SOI films also are more tolerant of manufacturing variations and offer more predictable behaviour. Non-uniform self-heating within the drift region has been measured for the first time. A breakdown voltage of 1020 V is reported for a LDMOS transistor made in a 0.15 /spl mu/m SOI layer.
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The optimization of the floating-ring parameters and the breakdown voltage of a lateral DMOS (LDMOS) transistor using a single floating ring is presented. A first-order analytical approach is presented, showing the upper limit of the position of the ring, with respect to the channel, and the doping concentration within the ring to increase the breakdown voltage. A 2D numerical calculation of the breakdown voltage and on-resistance of the LDMOS transistor is also presented. The results, which support the analytical approach, allow the use of simple design rules for the implementation of high-voltage LDMOS transistors on a thick epitaxial layer. It is shown that improvements of breakdown voltage is obtained if the distance between the channel and the field ring is equal to the field plate length and the doping concentration in the ring satisfies a specific relationship. With a single ring, the breakdown voltage increases from 170 to 280 V for the same device area and to over 480 V if the area is allowed to increase by 25%.< >
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Transistor model
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Figure of Merit
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LDMOS
Depletion region
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This paper presents a new adaptive resurf (reduced surface field) concept for 20 V LDMOS which introduces an additional resurf layer to the conventional resurf layer. The new resurf LDMOS achieves a sufficiently low on-resistance of 17.7 m/spl Omega//spl middot/mm/sup 2/ and a high static breakdown voltage of 28.0 V without significant breakdown voltage degradation under large drain current flow conditions. The device on-state breakdown voltage for a 5 V gate voltage is 21.8 V.
LDMOS
Degradation
Power MOSFET
High Voltage
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