A wafer-level 3-D integration scheme using Cu through-silicon vias (TSVs) and fine-pitch Cu/Sn-BCB hybrid bonding was developed and investigated with electrical characterization and reliability assessment. The hybrid bonding could be achieved below 250 °C. Low Kelvin resistance and stable daisy chain resistance were achieved in 5- and 10- μm TSV test structures across the whole wafer. Without obvious deterioration in reliability test results, the integrated Cu TSV and hybrid bond scheme can be potentially designed for 3-D integration applications.
In this paper, a 3D chip-to-chip hetero-integration scheme without Si interposer is demonstrated under 270°C thermal budget. The scheme successfully integrates advanced and common technology node logic chips by Cu/Sn to ENIG bumping. Cu/Sn μ-bumps are electroplated on common technology node and ENIG joints are electroless-plated on advanced technology node opening pads, respectively. Herein, 60 μm bump pitch, 40 μm diameter of Cu/Sn μ-bump and 50 μm diameter of ENIG are presented. Without cracks and voids, the 3D C2C scheme gives an efficient approach for future development of 3D IC.
In this work, a particular ultra-thin buffer layer (UBL) with various thickness ranging from 10 nm to 100 nm and different materials including Co, Ni, Pd and Ti is inserted between Cu/Sn to delay the interdiffusion prior to eutectic bonding. The efficacy of the buffer layer and the bonding quality are systematically conferred using microstructure imaging, material analysis, and electrical performance. In addition to symmetric Cu/Sn bonding with UBL, an asymmetric Cu/Sn-Cu bonding which is proposed to relieve the heat-enhanced interdiffusion issues thereby enhancing the reliability performance is demonstrated with the assistance of UBL technology.
A high yielding fine-pitch submicron Cu/Sn bonding scheme has been successfully demonstrated. With inserting the ultra-thin buffer layer, near sub-micron thickness Cu/Sn pad bonding can be achieved. The fine pitch Cu/Sn interconnects can be also further extended. The modified Kelvin feature in chip level and tens of thousands series interconnects per chip with a density of 3.4 × 10 5 /cm 2 in wafer level are fabricated and completely investigated on electrical characteristics. Several critical reliability assessments, such as TCT and un-bias HAST, are also investigated the variation and standard error of the fine-pitch pad bonding scheme. With excellent mechanical properties, bonding quality, electrical and reliability results, the approach is suitable for future 3D vertical interconnects.
The quality of germanium (Ge) epitaxial film grown directly on silicon (Si) substrate is investigated based on the electrical properties of a metal-oxide-semiconductor capacitor (MOSCAP). Different thermal cycling temperatures are used in this study to investigate the effect of temperature on the Ge film quality. Prior to high- k dielectric deposition, various surface treatments are applied on the Ge film to determine the leakage current density using scanning tunneling microscopy. The interface trap density ( Dit ) and leakage current obtained from the C - V and I - V measurements on the MOSCAP, as well as the threading dislocation density (TDD), show a linear relationship with the thermal cycling temperature. It is found that the Ge epitaxial film that undergoes the highest thermal cycling temperature of 825 ° C and surface treatment in ultraviolet ozone, followed by germanium oxynitride (GeO x N y ) formation, demonstrates the lowest leakage current of ~ 2.3×10 -8 A/cm 2 (at -2 V), Dit ~ 3.5 × 10 11 cm -2 /V, and TDD <; 10 7 cm -2 .
A novel 3-D chip-level heterogeneous integration scheme for low cost and rapid pilot demonstration is proposed in this paper. The conventional Bumping fabrication is done at wafer level. However, due to the high cost of whole wafer, opting for chips with advanced technology node is a better alternative. Therefore, with the difficulties of the bumping process at chip level, 3-D heterogeneous integration by chip stacking faces challenges. This paper presents a novel heterogeneous integration platform by using electroless plating on chips and pillar bump on wafers before stacking. This integration platform can be applied to chip-to-chip or chip-to-wafer scheme when chips are fabricated from costly advanced technology node.
The demand of small-feature-size, high-performance, and dense I/O density applications promotes the development of fine-pitch vertical interconnects for 3-D integration where microbumps are fabricated with Cu through-silicon via and under-bump metallization. Small dimension Cu/Sn bonding has to be developed to address the needs of increasing I/O density and shrinking pitch and size for future applications. For fine-pitch microbumps, it is important to select right UBM and solder materials to obtain lower UBM consumption, which means lower intermetallic compound (IMC) thickness. To find the best binary system material for fine-pitch microbumps with a different annealing temperature and time, we investigate the interfacial reaction and intermetallic compound morphologies of Co UBM with Sn, SnCu, and SAC solders. A thin, uniform, and single-phase IMC between solder and UBM facilitates finer pitch and more reliable microbumps development; the higher activation energies imply longer solder lifetime. Co, as an ultrathin buffer layer (UBL), is also used in Cu/Sn bonding. A comparison between Cu-Sn bonding with and without UBL is conducted. From this study, Co as UBL and UBM is explored and could be applied in semiconductor applications.
Wafer-level Sn/In-Cu bonding structure with Ni ultra-thin buffer layer is investigated to achieve a reduction in solder thickness, bonding temperature and duration. Furthermore, the asymmetric bonding structure is able to separate the manufacturing process of solder and electrical isolation layer. It is a promising approach for the application on hybrid bonding of three-dimensional integration.
In this paper, the wafer-level three-dimensional (3-D) integration scheme using copper TSVs and fine-pitch Cu/Sn-BCB hybrid bonding is designed, fabricated, and completely investigated on electrical characteristics and stability. Key technologies in this 3D integration scheme include high aspect-ratio Cu TSV, fine-pitch Cu/Sn micro-bumps, 250°C low temperature hybrid bonding, wafer thinning and backside RDL formation. The Kelvin and leakage current structures are designed for realization of fundamental electrical properties, and the daisy chain feature is designed for stability evaluation with several reliability tests. All the samples pass the 1000-cycle thermal cycling test, humidity test, and multiple AC current stressing. This scheme shows a significant leakage current improvement after modifying backside process. The stable reliability results and excellent electrical characteristics indicate that the 3D integration scheme has the excellent sealing ability against oxidation and corrosion, and could be potentially applied for future mass production.
Data replication is an important issue in distributed systems. Many protocols are designed to achieve high availability, but some of them have restrictions on N, the number of nodes in the system. This motivates us to design a protocol suitable for arbitrary N. In this paper, we present a new quorum-based replica control protocol whose quorum size is O(/spl radic//N), which is the same as that of the grid protocol. Moreover; the proposed protocol is almost symmetric, i.e., each node nearly bears the same responsibility. In particular, our protocol performs well in systems where read operations are requested more frequently than write ones.
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