Electrical and Reliability Investigation of Cu TSVs With Low-Temperature Cu/Sn and BCB Hybrid Bond Scheme
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Abstract:
A wafer-level 3-D integration scheme using Cu through-silicon vias (TSVs) and fine-pitch Cu/Sn-BCB hybrid bonding was developed and investigated with electrical characterization and reliability assessment. The hybrid bonding could be achieved below 250 °C. Low Kelvin resistance and stable daisy chain resistance were achieved in 5- and 10- μm TSV test structures across the whole wafer. Without obvious deterioration in reliability test results, the integrated Cu TSV and hybrid bond scheme can be potentially designed for 3-D integration applications.Keywords:
Daisy chain
Three-dimensional integrated circuit
Through-Silicon Via
This paper presents a survey of 3D Integrated Circuits using Through Silicon Vias (TSV). 3D Integrated Circuits and the TSV will be defined, the rationale for moving to these systems will be given, and an overview of the construction of the 3D Integrated Circuit and TSV will be presented. Lastly, the challenges for 3D Integrated Circuits using TSVs will be discussed.
Through-Silicon Via
Three-dimensional integrated circuit
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With through silicon via(TSV) area scale factor r,an analytical thermal model for top layer of three-dimensional integrated circuits(3D IC) taking TSV into account was proposed.It is shown that temperature is lower after considering TSVs under same working conditions;the greater the scale factor r,the lower the temperature is;For more layers and smaller r,temperature increases sharply with decrease of r;The best range of TSV area ratio factor r is 0.5% to 1% for an 8-layer 3D IC.
Through-Silicon Via
Three-dimensional integrated circuit
Scale factor (cosmology)
Atmospheric temperature range
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3D integration consists of 3D integrated circuit (IC) packaging, 3D Si integration, and 3D IC integration. They are different and in general the through-silicon via (TSV) separates 3D IC packaging from 3D Si/IC integrations since the latter two use TSV but 3D IC packaging does not. 3D Si integration and 3D IC integration are different. 3D IC integration stacks up the thin chips with TSV and microbump, while 3D Si integration stacks up thin wafers with TSV alone (i.e., bumpless). TSV is the heart of 3D Si/IC integrations and is the focus of this investigation. Also, the state-of-the-art, challenge, and trend of 3D integration will be presented and examined. Furthermore, supply chain readiness for high volume manufacturing (HVM) of TSVs is discussed.
Three-dimensional integrated circuit
Through-Silicon Via
Integrated circuit packaging
Vertical Integration
System Integration
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Three-dimensional integrated circuit
Through-Silicon Via
Vertical Integration
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Three-dimensional integrated circuits (3D ICs) are the IC chips with multiple device layers stacked together with various vertical interconnect technologies. The layers could be connected with wire-bonding, through-silicon-vias (TSV), microbump, or even ...
Three-dimensional integrated circuit
Through-Silicon Via
Wire bonding
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Three-dimensional integrated circuits (3D ICs) are the IC chips with multiple device layers stacked together with various vertical interconnect technologies. The layers could be connected with wire-bonding, through-silicon-vias (TSV), microbump, or even inductive/capacitive contact.
Three-dimensional integrated circuit
Through-Silicon Via
Wire bonding
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D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They are different and in general the TSV (through-silicon via) separates 3D IC packaging from 3D IC/Si integrations since the latter two use TSV but 3D IC packaging does not. TSV (with a new concept that every chip or interposer could have two surfaces with circuits) is the heart of 3D IC/Si integrations and is the focus of this investigation. The origin of 3D integration is presented. Also, the evolution, challenges, and outlook of 3D IC/Si integrations are discussed as well as their road maps are presented. Finally, a few generic, low-cost, and thermal-enhanced 3D IC integration system-in-packages (SiPs) with various passive TSV interposers are proposed for high performance applications.
Three-dimensional integrated circuit
Interposer
Through-Silicon Via
Integrated circuit packaging
Vertical Integration
System Integration
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Citations (9)
3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They are different and in general the TSV (through-silicon via) separates 3D IC packaging from 3D IC integration and 3D Si integration since the latter two use TSV but 3D IC packaging does not. TSV (with a new concept that every chip could have two surfaces with circuits) is the focus of this investigation. State-of-the-art, key differences, trends of these three technologies, and a 3D integration roadmap are presented.
Three-dimensional integrated circuit
Through-Silicon Via
Integrated circuit packaging
System Integration
Vertical Integration
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Citations (8)
3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They are different and in general the TSV (through-silicon via) separates 3D IC packaging from 3D IC/Si integrations since the latter two use TSV but 3D IC packaging does not. TSV (with a new concept that every chip or interposer could have two surfaces with circuits) is the heart of 3D IC/Si integrations and is the focus of this investigation. The origin of 3D integration is presented. Also, the evolution, challenges, and outlook of 3D IC/Si integrations are discussed as well as their road maps are presented. Finally, a few generic, low-cost, and thermal-enhanced 3D IC integration system-in-packages (SiPs) with various passive TSV interposers are proposed.
Three-dimensional integrated circuit
Interposer
Through-Silicon Via
Integrated circuit packaging
Vertical Integration
System in package
System Integration
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This paper applies the carbon materials (i.e., SWCNT, MWCNT, and GNR) as new prospective filler materials of through silicon vias (TSV) for replacing the conventional copper (Cu) to improve the thermal performance of three-dimensional integrated circuits (3-D ICs). The thermal performance of 3-D ICs with integrated TSVs is investigated and the corresponding numerical calculation model is established in this work. Moreover, the thermal performance of 3-D ICs with integrated carbon materials based TSV is investigated by applying our proposed numerical calculation model. The calculation results illustrate that the 3D-ICs with integrated SWCNT based TSV have a greater thermal performance, as compared with the 3-D ICs integrated other materials (i.e., MWCNT, GNR, and Cu) based TSV. Furthermore, it is also manifested that the temperature of die layer in 3-D ICs can be reduced by increasing the thermal conductivity of package and heat sink, by increasing the radius of TSV and decreasing the spacing between TSV. In addition, it is found that the results of our proposed numerical calculation model are fairly consistent with COMSOL simulation and the maximum relative error for them is not exceeding 2%. The proposed new filler materials in this work has many potential applications in improving the heat dissipation performance of 3-D ICs, meanwhile the presented numerical calculation model can provide guidelines for thermal design of 3-D ICs.
Three-dimensional integrated circuit
Through-Silicon Via
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