The Virginia Power Electronics Center at Virginia Tech has developed a low cost approach for packaging of power electronics building blocks (PEBB) consisting of power semiconductor devices, drivers, controls, sensors and protection circuits for a wide range of power electronics applications, such as inverters for motor drives and converters for power processing equipment. The new concept of PEBB packaging, termed metal posts interconnected parallel plate structure (MPIPPS), is based on direct bonding of copper posts to interconnect power devices, thus eliminating wire-bonding with aluminum wires. The interior space between the parallel plates and copper posts can be used as a flow channel for heat dissipation by a dielectric fluid, or filled with a solid or liquid for additional heat spreading. This approach requires less expensive processing equipment and has the potential to produce cost-effective high power modules that have superior electrical, thermal, and mechanical performance. This paper presents the materials selection and fabrication techniques developed in the course of the research and initial electrical and thermal characterization of the MPIPPS structure.
In this work, miniaturization of Coplanar waveguide (CPW) fed slot antenna loaded with loop is presented. In addition to that, it is also possible to further reduce the resonant frequency with proper loading of circular loop and cylindrical Dielectric Resonator (DR). The unloaded and loaded resonance frequencies are 4.46 GHz and 2.23 GHz respectively which results in 50% reduction in resonant frequency without effecting radiation characteristics. But, with only loop loading on either end of radiating slot exhibits 19.50% reduction in resonance frequency. We also introduced hollow cylindrical dielectric resonator in loop loading antenna topology in that case we got 29.37% miniaturization in resonant frequency. Also after loading efficiency of loaded antenna structure improves slightly compare to reference antenna.
The design of a miniaturized slot antenna based on wire-loading is presented. The miniaturization can be achieved with minimal increase in the lateral space along the slot width. Both the cases of a slot antenna on dielectric substrate and a slot antenna on ground plane are considered. For the former case, a miniaturization of 28.83% is achieved. The radiation characteristics of the size-reduced antenna are almost similar to the unloaded slot, with low cross-polarization levels. For the slot antenna on a ground plane, the miniaturization is affected by a cavity-backed design with the loading wires penetrated into the cavity. A 45.52% reduction in resonant frequency is achieved relative to the unloaded slot. The radiation characteristics in the upper hemisphere are almost unperturbed compared to the unloaded slot.
In this paper, the effect of four different types of loops—circular, semicircular, square loop, and semi-square loop in the presence of a conducting cone are presented. The isolated loop has very poor matching characteristics. In presence of a conducting cone, the mutual coupling between the loop and the conducting cone are responsible to improve the matching characteristics. Circular and square loops have the equal circumference (157 mm), whereas semicircular and semi-square loops have half the assigned circumference. Semicircular and semi-square loops also have unchanged matching characteristics. The measurement results are also proffered to validate the results. The radiation patterns are also shown for each loop antenna topology in presence of a conducting cone.
The research presented in this paper is part of a multidisciplinary research program of Virginia Power Electronics Center (VPEC). The program supported by the Office of Naval Research (ONR) focuses on the development of innovative technologies for packaging power electronics building blocks (PEBBs). The primary objective of this research is to improve package performance and reliability through thermal management, i.e. reducing device temperatures for a given power level. The task of thermal management involves considering trade-offs in the electrical design, package layout and geometry, materials selection and processing, manufacturing feasibility, and production cost. Based on the electrical design of a simple building block, samples of packaged modules, rated at 600 V and 3.3 kW, were fabricated using a stacked-plate technique, termed metal posts interconnected parallel plate structure (MPIPPS). The MPIPPS technique allows the power devices to be interconnected between two direct-bond copper substrates via the use of metal posts. Thus, heat dissipation by conduction from both sides of a module is achievable. Furthermore, for more aggressive heat removal, the interior space of a module between the parallel substrates can be used as a channel for a dielectric liquid flowing over the devices. Thermal test and modeling results on the MPIPPS packaged modules indicate that the new packaging technique offers a superior thermal management means for packaging power electronics modules.
Major MOSFET manufacturers have recently introduced innovative packaging options to achieve the next level of breakthroughs in electrical and thermal performance. Some of the innovations involve replacement of wire-bonds with solder-bumps for device interconnections in power devices and reduction in number of interfaces/paths for heat dissipation. The overall goal is to achieve small form factor MOSFET packages with significant improvements in electrical and thermal performance. This paper outlines the recent trends in MOSFET packaging and provides package-level thermal modeling results of wire-bond, strap bond, flipchip, ball-grid-array, and micro-lead-frame based packages. It also highlights the critical issues related to the processing, cost and reliability of such packages, which must be addressed before the conventional lead-frame based discrete solutions can be replaced with the new ones. Fundamental cooling mechanisms associated with different packaging technologies for MOSFETs are investigated. The impact of the internal package design on thermal performance is discussed in detail. The role of underfill materials in flip chip and BGA applications is also addressed.
Virginia Power Electronics Center (VPEC) has developed a stacked-plate technique for 3-D packaging of power electronics building block modules. A basic building block-a two-switch two-diode half-bridge converter in totem-pole configuration with built-in gate-driver and protection circuitry, fiber-optic receiver/transmitter interface, and soft-switching capability has been constructed. This innovative packaging technique uses high-performance copper/aluminum nitride/copper sandwiched plates as substrates for power devices. To interconnect the devices, metal posts are soldered directly onto the devices instead of using wire bonding. Test and modeling results of the packaged modules showed the potential for low parasitics, excellent thermal management, and improved reliability.
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