Kwang‐Ting Cheng

University of Hong Kong

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Document Type

Co-Authors

Xin Yang

Shanghai Jiao Tong University

Li-C. Wang

University of California, Santa Barbara

Zechun Liu

META Health

Tsung‐Ching Huang

Hewlett-Packard (United States)

A. Krstić

Universidade Federal Fluminense

Zengqiang Yan

Huazhong University of Science and Technology

Jing-Jia Liou

National Tsing Hua University

Shi‐Yu Huang

Wuhan University

Vishwani D. Agrawal

Auburn University

Hao Chen

Guangdong Medical College

Cooperative Institutions

Weatherford College

403

Istituto Tecnico Industriale Alessandro Volta

351

University of Washington

289

National Center on Birth Defects and Developmental Disabilities

197

University of Hong Kong

178

Chinese Academy of Sciences

152

University of California, Santa Barbara

146

Seattle University

139

Seattle Children's Hospital

139

Hong Kong University of Science and Technology

111

Author Statistics

Papers

Citation

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Research Field

Stereo Neural Vernier Caliper

arXiv (Cornell University) (2022)

Shichao Li Zechun Liu Zhiqiang Shen Kwang‐Ting Cheng

We propose a new object-centric framework for learning-based stereo 3D object detection. Previous studies build scene-centric representations that do not consider the significant variation among outdoor instances and thus lack the flexibility and functionalities that an instance-level model can offer. We build such an instance-level model by formulating and tackling a local update problem, i.e., how to predict a refined update given an initial 3D cuboid guess. We demonstrate how solving this problem can complement scene-centric approaches in (i) building a coarse-to-fine multi-resolution system, (ii) performing model-agnostic object location refinement, and (iii) conducting stereo 3D tracking-by-detection. Extensive experiments demonstrate the effectiveness of our approach, which achieves state-of-the-art performance on the KITTI benchmark. Code and pre-trained models are available at https://github.com/Nicholasli1995/SNVC.

Benchmark (surveying)

Code (set theory)

Cuboid

Calipers

10.48550/arxiv.2203.11018

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Citations (0)

AutoDCIM: An Automated Digital CIM Compiler

Jia Chen Fengbin Tu Kunming Shao Fengshi Tian Xiao Huo

Digital Computing-in-Memory (DCIM) is an emerging architecture that integrates digital logic into memory for efficient AI computing. However, current DCIM designs heavily rely on manual efforts. This increases DCIM design time and limits the optimization space, making it challenging to satisfy the user specifications of diverse AI applications. This paper presents AutoDCIM, the first automated DCIM compiler. Au-toDCIM takes the user specifications as inputs and generates a DCIM macro architecture with an optimized layout. AutoDCIM's template-based generation balances handcrafted cell design and agile macro development. AutoDCIM's layout exploration loop analyzes diverse DCIM array partitioning schemes to satisfy user specifications. The auto-generated DCIM macros present competitive efficiency results in comparison with state-of-the-art silicon-verified DCIM macros.

Macro

10.1109/dac56929.2023.10247976

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Citations (3)

Design of sequential machines for efficient test generation

Kwang‐Ting Cheng Vishwani D. Agrawal

The authors propose design for testability at the logic synthesis level. Their state assignment is aimed at producing a reduced feedback or pipeline like structure which is easily analyzed by a sequential circuit test generator. State variables are assigned one at a time such that a state variable depends only on primary inputs and the previously assigned state variables. This results in a purely pipeline structure for finite-memory or definite machines. For other machines, the number of cycles in the implemented structure is minimized. The authors give several examples to compare their reduced feedback synthesis with another method that is aimed at reducing the amount of logic in a multilevel implementation. Results show a marked improvement in test generation time and fault coverage; in terms of logic their method did just as well as the other method.< >

Sequential logic

Design for testing

10.1109/iccad.1989.76969

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Citations (29)

Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models

A. Krstić Li-C. Wang Kwang‐Ting Cheng J.-J. Liou Terrence Mak

In this paper, we propose a new methodology for diagnosis of delay defects in the deep sub micron domain. The key difference between our diagnosis framework and other traditional diagnosis methods lies in our assumptions of the statistical circuit timing and the statistical delay defect size. Due to the statistical nature of the problem, achieving 100% diagnosis resolution cannot be guaranteed. To enhance diagnosis resolution, we propose a 3-phase diagnosis methodology. In the first phase, our goal is to quickly identify a set of candidate suspect faults that are most likely to cause the failing behavior based on logic constraints. In the second phase, we obtain a much smaller suspect fault set by applying a novel diagnosis algorithm that can effectively utilize the statistical timing information based upon a single defect assumption. In the third phase, our goal is to apply additional fine-tuned patterns to successfully narrow down to more exact suspect defect locations. Using a statistical timing analysis framework, we demonstrate the effectiveness of the proposed methodology for delay defect diagnosis, and discuss experimental results based on benchmark circuits.

Benchmark (surveying)

Suspect

Static timing analysis

Statistical Analysis

10.1145/775832.776001

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Citations (34)

Trustworthy ICs for secure embedded computing

IEEE Design & Test of Computers (2007)

Kwang‐Ting Cheng

The design of secure and trusted embedded systems has recently drawn enormous attention from system-design practitioners. A secure system is only as strong as the weakest link. Therefore, any security functions implemented in an embedded system must be considered in both hardware and software, at all design abstraction levels, in communications between components, and in the manufacturing phase. In addition, these implementations are subject to typical power, performance, and cost constraints of consumer embedded systems. This issue of IEEE Design & Test features a special issue on Design and Test of Integrated Circuits for Secure Embedded Computing.

Implementation

Abstraction

Trustworthiness

10.1109/mdt.2007.207

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Citations (0)

Incremental Logic Rectification

Frontiers in electronic testing (1998)

Shi‐Yu Huang Kuang-Chien Chen Kwang‐Ting Cheng

10.1007/978-1-4615-5693-0_11

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Citations (15)

Improving validation coverage metrics to account for limited observability

Peter Lisherness Kwang‐Ting Cheng

In both pre-silicon and post-silicon validation, the detection of design errors requires both stimulus capable of activating the errors and checkers capable of detecting the behavior as erroneous. Most functional and code coverage metrics evaluate only the activation component of the testbench and ignore propagation and detection. In this paper, we summarize our recent work in developing improved metrics that account for propagation and/or detection of design errors. These works include tools for observability-enhanced code coverage and mutation analysis of high-level designs as well as an analytical method, Coverage Discounting, which adds checker sensitivity to arbitrary functional coverage metrics.

Observability

Code coverage

Code (set theory)

10.1109/aspdac.2012.6164962

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Citations (3)

Self-testing second-order delta-sigma modulators using digital stimulus

Chee-Kian Ong Kwang‐Ting Cheng

Single-bit second-order delta-sigma modulators are commonly used in high-resolution ADCs. Testing this type of modulator requires a high-resolution test stimulus, which is difficult to generate. This paper proposes a novel and robust technique to determine the performance of the modulator, which incorporates simple design-for-testability circuitry. This technique requires only digital stimulus to test the modulator. Hence, it is suitable as an analog signature analyzer used in built-in self-test applications. Simulation results show that this technique is capable of accurately determining the performance of a second-order delta-sigma modulator ADC.

Delta-sigma modulation

Stimulus (psychology)

10.1109/vts.2002.1011122

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Citations (17)

PBIR

Edward Yi Chang Kwang‐Ting Cheng Wei-Cheng Lai Ching-Tung Wu Chengwei Chang

We describe the Perception-Based Image Retrieval (PBIR) system that we have built on our recently developed query-concept learning algorithms, MEGA and SVMActive. We show that MEGA and SVMActive can learn a complex image-query concept in a small number of user iterations (usually three to four) on a large, multi-category, high-dimensional image database.

Mega-

10.1145/500141.500260

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Citations (11)

BER Estimation for Linear Clock and Data Recovery Circuit

Lecture notes in electrical engineering (2009)

Dongwoo Hong Kwang‐Ting Cheng

SIGNAL (programming language)

10.1007/978-90-481-3443-4_3

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Citations (0)